1. Field of the Invention
The present invention relates to a tool for integrated circuit design. In particular, the present invention relates to a tool for optimizing the physical design of a standard cell-based integrated circuit for performance.
2. Discussion of the Related Art
A standard cell-based integrated circuit is designed using a library of building blocks, known as “standard cells.” Standard cells include such elements as buffers, logic gates, registers, multiplexers, and other logic circuits (“Macros”).
FIG. 1a shows a typical design process or “flow” 100 that an integrated circuit designer would use to design a standard cell-based integrated circuit. As shown in FIG. 1a, at step 101, the designer provides a functional or behavioral description of the integrated circuit using a hardware description language. In addition, the designer specifies timing and other performance constraints (109) with which the integrated circuit must comply. Then, at step 102, the designer selects a standard cell library to implement the design. Typically, the standard cells in the library are designed to the requirements of a target manufacturing technology. Often, each cell is also characterized to provide performance parametric values such as delay, input capacitance and output drive strength.
At step 103, the designer uses a “synthesis tool” to create from the functional or behavioral description a functionally equivalent logic gate-level circuit description known as a “netlist.” The elements of the netlist are instances of standard cells selected by the synthesis tool from the standard cell library in accordance with functional requirements and the performance constraints. At this stage, the synthesis tool uses the characteristic parametric values of each standard cell and a model of input and output loads (“wire load model” or “WLM”) to attempt to meet performance requirements.
At step 104, a “place and route” tool creates a “physical design” by placing the standard cell instances of the netlist onto the “silicon real estate” and routes conductor traces (“wires”) among these standard cell instances to provide for interconnection. Typically, the placement and routing of these standard cell instances are guided by cost functions, which minimize wiring lengths and the area requirements of the resulting integrated circuit.
At step 105, with the wires of the integrated circuit having been routed at step 104, a more accurate set of parasitic impedance values in the wires can be extracted. Using the extracted parasitic impedance values, a more accurate timing analysis can be run at step 106 using a static timing analyzer (STA). If the physical design meets timing constraints, the design process is complete (step 108). Otherwise, steps 103–106 are repeated after appropriate modifications at step 107 are made to the netlist and the performance constraints.
Design process 100 suffers from a number of disadvantages. First, WLM is a crude model based on statistics. Because of the inaccurate model, a designer typically uses an “80th percentile WLM” (i.e., 80% of the nets will have a capacitance less than predicted by the WLM). As a result, the drivers for many nets are unnecessarily large, while other driver are too weak. Additionally, designers tend to provide 30% or more additional safety margins to accommodate other inaccuracies in the design flow. Such over-design represents inefficiencies in both silicon area and performance. Second, under this typical method, whenever a non-trivial modification is made to the design to meet a performance requirement, the design is re-synthesised, re-placed and re-routed, which are very time-consuming and costly steps, even when timing is met in a majority of nets. Typically, at each iteration, the physical design undergoes major changes that may introduce new sub-optimal nets requiring another iteration of synthesis, placement and routing to correct.
The inefficiency in the prior art method results in both high cost and long development time in engineering, time-to-market and manufacturing.